- #How to do infinite persistance on saleae logic pro 8 full#
- #How to do infinite persistance on saleae logic pro 8 code#
You might be thinking that I'm being silly here, and my example doesn't make sense, since ROM is mostly used to store the code and any timing violations during opcode read would result in execution failure.That's quantum computing on 8-bit 80's hardware for you! If the value in RAM is 0x55 (0b01010101) and the one in ROM 0xAA (0b10101010) then all you need is one bit of the ROM cell read correctly for the test to pass! Even if ROM reads as 0x54 (0b01010100), having only single bit 0 correct, then the equality test will correctly fail, and you will not notice the violation! So, with timing violations your results can vary between alternate possibilities with different probabilities. Now, if the value is fully random (it can assume any of 256 values with equal probability), the equality occurs only once in 256 tests. How random is the value in 0x2000 - basically, what values can it assume depending on the logic behind the program? If there are just two values (like 0x00 and 0xFF) then the probability you catch the error is higher, so your code is less vulnerable to timing violation.How much can you violate the ROM timing for the code to work? Basically, how much can you push that read beyond ROM limits before it fails? Let's consider simple example (assuming ROM starts at 0x8000):Īs you can see, I'm reading RAM at address 0x2000 and comparing it against ROM value at 0x9000, jumping to not_equal label when the values differ. It's especially interesting in case of reading ROM memory, which usually will be the slowest part of your build (unless you connect LCD directly to the bus, that is). More moving parts means much more unexpected behaviour. When you consider more complex chips it gets even worse. You might be lucky to get response faster thanks to the random operation in the IC.
Can you? Sure, we have decoupling caps for that purpose exactly, but still, keep that in mind, it might matter! If the voltage drops below 4.5V threshold, propagation delay will be longer and valid response will appear on output later. Now, it's tempting to assume that the worst case possible scenario at room temperature should be around 15-18ns (taken from rows 4 and 7), but this assumption is valid only if you can guarantee that your operating voltage will not drop below 4.5V. Let's look at the NAND gate used in Ben's project: This is why in datasheets you have pessimistic values for each operation, and while these are not very important at slow CPU speeds, the faster you go, the more it matters. It's not like the access will always take the same amount of time, because both internal and external conditions might change the duration of the process. What's even worse, this dance is not deterministic. It might, just as well, be just random value that resembles the final value closely enough.
Anything that happens in between is pretty much random, and as with anything random, you can never assume that your result is the proper, final one. Usually the dance of currents and voltages takes from several to several dozens of nanoseconds. What happens in a chip like a simple NAND gate is that whenever voltages change on input pins (which, by the way, is also not that very instant!), there is very long and complicated process where different components of the circuit start responding to changing input, and they all do it in very analogue and illogical way. That part I'm sure of - integration and circuitry are still up for debate :) That's already good news, but in fact: where do all these timing restrictions come from and why? Well, our digital logic integrated circuits are not as digital as we would like them to be, nor are they logical. We have all done that at some point, and what we know for sure is that it didn't cause the universe to implode. Again, sorry for going into such basic details, but it might not be obvious for everyone it certainly wasn't obvious for me. Bus translation is not very difficult, and documentation quality can be worked around with enough research (remember what that word meant before Google?), but both of these challenges are all the harder with tight timing of 14MHz.īefore we get to the point where I can talk about specifics, I would like to cover one more thing on the subject: what is the timing violation, and how can that affect your build.
#How to do infinite persistance on saleae logic pro 8 full#
It's the beginners like myself that struggle with these things, so I'd rather write a bit more and make it more useful.Īs I wrote in my first post on the subject, all the other issues are secondary, but the timing is the key in running 65C02 at full advertised speed. Sorry if it had been a bit stretched, and maybe too beginner-friendly, but I guess for all the experts out there it's all common knowledge. This is the final part of the 14MHz series, but I'm sure it's not last entry about it.